Architect Labs Built a Production AI Chip From Scratch in Two Weeks Using Only AI

An AI system at Palo Alto startup Architect Labs designed, verified, programmed, and deployed a production-worthy AI accelerator from a human-written specification in under two weeks — and then used the language model running on that accelerator to discover timing improvements and kernel optimizations for its own successor. The accelerator, called Redwood, is currently running live Qwen3-0.6B inference on an AMD Versal FPGA. The full technical paper was submitted to arXiv on August 26 and Architect Labs made the announcement publicly on August 27.

Two human architects contributed only a high-level specification. From that document, the company's Architect Labs Platform autonomously generated the performance model, RTL design, UVM verification environments, formal proofs, firmware, drivers, and custom compute kernels — every artifact the chip needed to function. No human engineers intervened below the specification level. When the RTL was first loaded onto the FPGA, there were zero bugs found. Every block across the full SoC reached 95% code and functional coverage.

The achievement matters not merely because a chip was produced quickly. It matters because Architect Labs claims it has collapsed the software-to-silicon stack — the years-long, team-intensive, sequentially frozen process that defines semiconductor development — into a single optimization loop that can re-run from scratch in under 48 hours whenever the specification changes.

The Sim-to-Silicon Gap That Redwood Crosses

Prior demonstrations of AI-assisted chip design have remained limited to toy circuits: small RISC-V cores, narrow arithmetic datapaths, or AI-accelerated individual steps within a human-driven flow. None had been validated on physical hardware while running a modern multi-billion-parameter language model. The academic community working on agentic electronic design automation had a name for this problem: the sim-to-silicon gap. A 2024 survey of agentic EDA explicitly identified it as the central criticism of the field — simulation results and RTL that passes functional verification are real but insufficient. Hardware is the final constraint, and hardware had not been demonstrated.

The history of AI in chip design is instructive. DeepMind's AlphaChip demonstrated reinforcement learning for chip floorplanning — optimizing the physical placement of functional blocks within an existing design — and reached production deployment at Google. That was a meaningful result, but placement is one step in a process that spans architecture definition, RTL coding, functional verification, synthesis, physical design, timing closure, and backend signoff. Each of those steps normally requires separate specialized engineering teams. AlphaChip automated one. The EDA industry's response over the last several years — Cadence, Synopsys, Siemens all adding AI agents to their existing platforms — has largely followed the same model: accelerate individual steps within a flow that remains fundamentally sequential and human-orchestrated.

Redwood's claim is different in kind. Architect Labs is not accelerating steps in an existing flow. It is replacing the flow itself with a single optimization loop that generates all steps in parallel from a common specification. Whether that distinction holds up under the scrutiny of a full ASIC tapeout, with the physical design complexity that fabricated silicon introduces, remains the open question the company intends to answer.

Redwood crosses the FPGA hardware line, partially. It runs on an AMD Versal VPK180 FPGA at 250 MHz — not fabricated silicon — and delivers 12.1 tokens per second on average when running Qwen3-0.6B end-to-end, including prompt transfer from a host processor and per-token streaming back. The company demonstrated the system running live at this summer's Design Automation Conference in Long Beach, California, where it was among the very few exhibitors showing an AI-designed accelerator executing model inference on physical hardware.

A tapeout on TSMC is planned but has not occurred. All comparisons to NVIDIA's Jetson Orin Nano on a Samsung 8 nm process class are architectural projections derived from measured FPGA data and a gate-equivalent area methodology — not measured silicon results. Architect Labs is transparent about this in its technical paper, stating that "real silicon is the final ground truth." The gap between FPGA demonstration and ASIC tapeout remains the central open question.

How the Architect Labs Platform Generates Hardware From a Spec

Traditional chip design is governed by freezes. An architecture team defines the system, freezes it, and hands off to microarchitecture. That team freezes and hands to RTL design. RTL hands to verification. Verification hands to physical design. At each handoff, upstream changes become increasingly expensive and eventually impractical. This sequential pipeline enforces approximately 9-to-12-month generation cadences at large semiconductor companies, with the total design-to-silicon process spanning one to two years.

Architect Labs eliminates the freeze concept. Its platform — ALP — treats a human-written specification as the single source of truth from which every artifact is generated in parallel. When an architect adjusts the spec, ALP regenerates RTL, re-runs formal verification, rebuilds firmware, reoptimizes kernel schedules, and revalidates coverage automatically. Architect Labs states that each architectural iteration during the Redwood project was fully regenerated, reverified, and redeployed to the FPGA within 48 hours.

The verification process within ALP represents a meaningful departure from how most "AI for verification" tools work today. Standard AI-assisted verification keeps a human design verification engineer at the center, using AI to accelerate test-case generation and testbench construction — a workflow that still requires significant human effort and does not materially shorten the end-to-end cycle. In ALP's approach, every testbench, test case, formal artifact, and simulation for Redwood was generated automatically from the specification using AI and compiler-based methods, with no human DV participation. The company built its own proprietary formal engine that generates sections of each verification environment directly from the human-written spec and then measures and optimizes its own coverage criteria.

During the Redwood project, the AI system peaked at 115 merge commits in a single day. A custom FPGA emulation environment multiplexed access to the physical board across hundreds of concurrent agents simultaneously, cutting individual optimization runs from 15 hours to roughly 15–30 minutes.

The economics implied by this timeline are significant. A traditional ASIC design program at the complexity level of Redwood — a production SoC with complete RTL, formal verification, firmware, and custom kernels — would typically engage a team of 10 to 30 engineers across hardware design, design verification, firmware, and physical design, working over 12 to 18 months. At current engineering labor rates for senior chip designers in the United States, that corresponds to tens of millions of dollars before a single wafer is processed. Architect Labs executed the equivalent work with two human architects in three weeks. The cost model for custom silicon, if the approach scales, changes structurally rather than incrementally. This is the underlying rationale for the company's Fortune 500 partnerships — custom silicon that previously required a dedicated internal chip team or an expensive ASIC design services firm could, in principle, be commissioned from a specification in weeks rather than derived from a multi-year development program.

Read more: Verification, Not Capability, Is the Bottleneck Holding Agentic AI Back

Redwood's Tile Architecture and the Memory Wall It Runs Into

Redwood is a tile-based, spatial-dataflow accelerator. Its compute fabric is an N×M mesh of identical tiles, each paired with edge DMA engines and connected through a credit-based, internally designed network-on-chip that supports broadcast, multicast, and per-link flow control. The AXI4 memory interface is confined to modular DMA engines, meaning Redwood can be integrated into a larger SoC, retargeted to CHI or ACE protocols without modifying the compute fabric, or packaged as a standalone chiplet.

Each tile is divided into a control front-end and a compute back-end. The front-end runs a RISC-V-based tile control core that operates in a slower clock domain and can power down entirely during kernel execution — a design choice that supports aggressive power gating. The back-end contains the matrix engine, which provides systolic GEMM and GEMV datapaths built from arrays of INT8 multiply-accumulate units, and the vector engine, which handles SIMD operations, transpose, and floating-point activations including the softmax function. Each tile shares a local 512-kilobyte scratchpad memory across these units via a high-bandwidth bus.

In the Redwood Nano configuration — the 2×2 tile array deployed on the FPGA — the matrix engine contains four tiles with 64 INT8 multiply-accumulate lanes each. At 250 MHz, this yields a peak generalized matrix-vector multiplication rate of 128 gigaoperations per second. The 512-bit SIMD datapath processes 32 BF16 or 16 INT32 operands per cycle. One significant hardware-software co-design choice: Redwood implements the softmax algorithm from FlashAttention-4 using existing SIMD resources rather than dedicating separate hardware. On a chip where area is finite, reusing units for an otherwise area-expensive operation is a meaningful tradeoff — this is the kind of optimization that becomes possible when firmware and RTL are designed simultaneously.

The roofline analysis in the paper is instructive about where performance actually lives. Running Qwen3-0.6B on this hardware, the memory service time per token is 3.6 times the arithmetic service time. Decoding is strongly memory-delivery-bound. The FPGA configuration achieves 16 GB/s of external memory bandwidth over four 128-bit AXI4 streams at 250 MHz, using LPDDR4. The NVIDIA Jetson Orin Nano uses LPDDR5 at 68 GB/s — more than four times the bandwidth. This disparity explains the gap between Redwood Nano's theoretical architectural ceiling of 21.73 tokens per second and its measured 12.1 tokens per second average. The memory bandwidth gap is a consequence of FPGA constraints, not of the accelerator's arithmetic design. In the projected ASIC configuration with memory bandwidth matching or exceeding the Jetson baseline, the memory-delivery bottleneck relaxes accordingly.

Recursive Self-Improvement Reaches Physical Hardware

The most significant result in the Redwood paper is not the 3.4x projected performance-per-watt advantage over the Jetson, nor the two-week design timeline. It is what happened in week three.

After Qwen3-0.6B was running live on Redwood Nano, Architect Labs exposed the model as an API endpoint inside its own AI system — the same system that had designed the accelerator. Through repeated sampling, the language model running on Redwood discovered timing improvements and kernel optimizations for several of its own operations at essentially zero inference cost. The model improved the hardware it was running on.

This constitutes what the paper describes as "one of the earliest demonstrations of recursive self-improvement": an AI system designs an AI accelerator, deploys a language model on it, and uses that model to improve the next generation of the accelerator. The I.J. Good framing — a machine capable of designing better machines, posited in 1965 — has historically described software intelligence. Here the loop extends to silicon.

The mechanism is worth describing precisely. Architect Labs exposed the running Qwen3-0.6B model as an API inference endpoint connected to the same AI system that produced the chip design. Through repeated sampling — asking the model to reason about its own timing behavior and kernel execution — the model produced optimization suggestions for several of its own operations. Critically, this happened at what the paper describes as "near-zero inference cost," meaning the optimization process did not require additional training runs or large-scale compute; the deployed model's standard inference capability was sufficient to find improvements in how its workload mapped to the accelerator's kernel scheduler and memory timing. The AI system then implemented those improvements, verified them, and redeployed to the FPGA within the standard 48-hour iteration cycle.

The caveat is scale. Qwen3-0.6B is a 600-million-parameter model — able to follow detailed reasoning tasks but not a frontier-capability system. The optimizations it found were timing improvements and kernel scheduling adjustments — real and valuable, but bounded by what a 0.6-billion-parameter model can reason about given operational visibility into its own hardware substrate. The gap between models capable of sophisticated hardware design reasoning (which currently require data center-class hardware to run) and models small enough to deploy on a specialized edge accelerator remains significant, as the paper illustrates in a diagram showing a mismatch between the "AI system capable of designing frontier hardware" and the "AI models that can actually deploy on that hardware." Closing this gap — by scaling the accelerator to larger models or improving the inference models' own hardware reasoning capabilities — is the research trajectory Architect Labs describes as its path forward.

Competing Against a Sequential Industry on an Asynchronous Timeline

Architect Labs sits in a competitive space that includes established EDA vendors adding AI capabilities and purpose-built AI-for-EDA startups. The distinction matters more than it might first appear.

Cadence's ChipStack positions itself as "agentic AI for SoC design." Siemens EDA announced at this year's Design Automation Conference an expansion of its strategic partnership with NVIDIA to build self-verifying agentic AI workflows within its Fuse EDA AI platform. Cognichip claims 10x productivity gains across RTL generation, verification, debugging, and exploration. According to Architect Labs' technical paper, ChipAgents has disclosed deployments with chip companies including Ambiq and Whalechip.

All of these approaches — including established vendor integrations — add AI within the existing sequential chip design flow. They accelerate individual steps: placement optimization, test-case generation, RTL debugging, lint checking. The sequential handoffs between teams and the architectural freeze points that define 18-month generation cadences remain structurally intact.

Architect Labs argues that task-level acceleration has not materially shortened end-to-end ASIC development time and cites the 2024 Wilson Research Group and Siemens EDA functional verification trend report, which found that only 14% of IC/ASIC projects achieve first-silicon success — the lowest rate in two decades — while 75% of chip programs are running behind schedule. If AI task acceleration alone were moving the needle, these statistics would be improving. They are not.

The company's alternative is orthogonal: eliminate the sequential structure, not accelerate it. From a single specification, the platform explores the architectural design space in parallel across hardware and software simultaneously. When a specification changes, every artifact is regenerated rather than patched. The design-to-hardware iteration cycle compresses to 48 hours. As available compute scales, the microarchitectural search space the system can explore expands — potentially beyond what any human team can enumerate. In the SIMD engine exploration documented in the paper, the AI system found candidate architectures with fundamentally different control paths and state machines, not merely bit-width adjustments, over a multi-day search that a human team covering the same space would require months to explore.

The company is already applying this approach with Fortune 500 partners, compressing programs that traditionally run for months into weeks — a claim it makes publicly but for which no named clients have been disclosed.

Read more: Anthropic Hires Google TPU Founder Amir Salek to Lead Custom Chip Push

Projected Performance and What Remains Unverified

Architect Labs projects Redwood's performance on a Samsung 8 nm-class process comparable to that used by the Jetson Orin Nano using two methodologies. Performance projections are derived from the FPGA roofline analysis, scaled for a 1 GHz logic clock and memory bandwidth matching the Jetson's LPDDR5 configuration. Area projections use a bottom-up gate-equivalent approach: 2 million combinational cells and 500,000 sequential registers weighted by average relative gate sizes, with 15% overhead for design-for-test logic, 70% placement utilization, and 20% area overhead for clock-tree-synthesis structures — yielding a projected NPU block area of approximately 2.88 square millimeters. Power projections separate dynamic and static components using standard industry modeling at 1 GHz on Samsung 8 nm at 0.75V nominal core voltage.

The projections produce a projected ASIC performance of 49 tokens per second at 1.335 watts, versus the measured Jetson baseline of 28 tokens per second at 2.59 watts — a 1.75x throughput improvement and 1.9x power reduction, combining to a 3.4x performance-per-watt gain.

These numbers are not silicon measurements. Every figure in the ASIC comparison is a model output calibrated from FPGA measurements, not a measurement from a fabricated chip. Roofline models are analytically rigorous tools, but they assume ideal conditions — full bandwidth utilization, no synchronization overhead, no process variation. Gate-equivalent area methodology is standard practice but does not account for memory layout effects, power delivery network overhead, or the yield challenges that can affect actual die size. The company acknowledges explicitly that "real silicon is the final ground truth" and has announced plans for full GDSII and a TSMC tapeout, but has not disclosed a timeline.

The single most important verification gap is the ASIC tapeout. If Redwood achieves its projections on silicon — or even a meaningful fraction of them — the implications for custom AI silicon economics are substantial. A 2.88 mm² edge AI accelerator at competitive throughput and power, produced in two weeks by two engineers from a specification, represents a fundamentally different cost structure for specialized silicon than the traditional 18-to-24-month, hundreds-of-engineers, hundreds-of-millions-of-dollars design cycle.

From Fabless to Designless: The Structural Claim

Architect Labs CEO Ebrahim Hussain has framed the company's long-term position using an analogy to the 1980s fabless semiconductor industry. When TSMC and other foundries made world-class manufacturing available to anyone with a chip design, companies that had no interest in owning manufacturing equipment — NVIDIA, Broadcom, Apple's chip teams — could build silicon businesses around design expertise alone. The manufacturing barrier fell, and a new competitive tier was born.

Hussain describes Architect Labs as "pioneering the designless semiconductor industry." In this model, an organization brings a workload — a target AI model, a robotics system, a specific edge inference application — and receives a chip co-designed with that workload, the way a fabless company brings a design to TSMC and receives wafers back. The chip design team that was previously the gate becomes a specification.

The company emerged from stealth with a $24 million seed round in June 2026, led by Kindred Ventures with participation from TQ Ventures, Race Capital, and Together Fund. Individual investors include Jeff Dean, who was then Google DeepMind's chief scientist and has since departed to co-found Discovery Loop, as well as Perplexity CEO Aravind Srinivas and semiconductor and AI executives from NVIDIA, Google, and OpenAI. Kindred Ventures founder Steve Jang joined the company's board.

The investment reflects a bet that the constraint on custom silicon will shift from manufacturing access — which TSMC largely solved — to design access, which remains expensive and slow. If ALP can reliably compress design programs and close to the verification standards that silicon requires, the addressable market is any organization that would benefit from specialized hardware but cannot sustain a traditional chip design organization. That includes robotics companies building physical AI systems, AI inference providers seeking edge-optimized deployments, enterprise operators running proprietary model workloads, and national defense programs requiring provenance-controlled silicon.

Whether the platform can scale from a 0.6-billion-parameter edge inference accelerator to the complexity of a state-of-the-art data center chip — with billions of transistors, heterogeneous integration, advanced node physical effects, and co-packaged optics — is the engineering challenge that the next generation of Redwood development will test. The recursive self-improvement loop that the current demonstration established gives Architect Labs a compounding advantage if the claim holds at scale: better AI models running on hardware that those models helped design, producing improved hardware for still-better models.

If silicon comes back from the foundry performing as projected, the question for the traditional EDA and ASIC design services industries will no longer be whether AI can meaningfully accelerate chip design. It will be whether the traditional design cycle can survive a competitor that replaces it entirely.