OpenAI's GPT-6 Astra Builds Complete Codex Hardware Device in Under a Week

Two OpenAI employees with no specialized hardware engineering background used GPT-6 Astra to produce a complete physical device — enclosure, printed circuit board, and embedded software — for interfacing with the company's Codex coding agent. The design took under a week. Working prototypes arrived from a contract manufacturer within a month. The project, described in an OpenAI blog post published November 4, represents the first documented case of a frontier language model driving an end-to-end hardware design from concept to manufacturable artifact — though the path to that manufacturer required multiple revision rounds after Astra's initial designs failed to meet factory tolerance constraints.

The demonstration is not a proof that AI has mastered physical engineering. What it establishes is narrower and more instructive: that GPT-6 Astra can close most of the gap between a software engineer and a first-pass hardware prototype, while the remaining gap — design-for-manufacturing compliance — still requires human review and iterative correction.

How the Work Was Divided Between GPT-6 and Astra

The project involved two distinct AI roles. GPT-6, OpenAI's standard reasoning model, generated functional requirements and an overall design specification. GPT-6 Astra — the company's top-tier multimodal reasoning model, priced at $10 per million input tokens and $50 per million output tokens — handled the engineering execution layer.

Astra designed the physical enclosure geometry, selected electrical components, performed PCB placement and trace routing, generated the embedded firmware, produced the user interface, and built the software integrations connecting the device to Codex. This division reflects the natural split in hardware engineering between specification (what the device needs to do) and implementation (how to make it manufacturable and functional).

The PCB design task alone covers substantial ground. Component selection requires cross-referencing availability, power budget, and footprint compatibility. Placement determines thermal performance and signal integrity. Trace routing must follow impedance requirements, avoid crosstalk, and clear manufacturing minimums for the specific fabrication process. Firmware, meanwhile, sits at the intersection of hardware constraints and software logic — a domain where code-generation models have made rapid gains.

The Manufacturing Gap: Where Astra's Designs Required Rework

Working prototypes existed within a month. Getting there required several iteration rounds.

Astra's initial designs failed to satisfy manufacturing tolerance constraints and assembly requirements — the category of physical limits that separate a geometrically correct design from one a factory can actually build at scale. These constraints, encoded in design rule check (DRC) files specific to each fabricator and in IPC industry standards, govern trace widths, via sizes, component clearances, solder mask expansion, and panelization keepout zones. A design that passes electrical simulation may still be unmanufacturable if its trace spacing falls below the fabricator's etching capability or its component placements violate assembly clearances.

This failure mode is well-documented in independent AI PCB research. The Atopile EEBench benchmark, which tests whether large language models can generate a fully-routed PCB from a schematic in KiCad format, recorded GPT-6 Astra completing 69.3% (±10%) of test cases at maximum reasoning effort — leaving roughly three in ten designs incomplete or incorrect. The Hackaday electronics community noted that production boards still require validation by multiple experienced engineers and must pass stringent testing before manufacture — framing the EEBench result as impressive progress, not engineering readiness.

The OpenAI demonstration does not contradict this picture. Manufacturing failures were acknowledged directly in the company's own documentation, and the multiple revision cycles serve as the article's most informative data point: AI-generated hardware designs currently need a human DFM review pass before the factory floor.

BenchCAD 2.0 and the Signal Hidden in OpenAI's Benchmark Disclosure

Alongside the hardware design demonstration, OpenAI published results from BenchCAD 2.0, an internal benchmark for evaluating AI performance on three-dimensional mechanical and PCB design tasks.

GPT-6 Astra at maximum reasoning effort scored 0.594. An unnamed internal OpenAI model scored 0.875.

BenchCAD 2.0 evaluates models on parametric CAD reconstruction — the ability to regenerate 3D mechanical parts such as gears, springs, and drill bodies from multi-view images, as well as PCB connection identification. Scores are measured by voxel Intersection-over-Union (IoU), which captures how well the AI-generated 3D shape spatially overlaps with the reference design. Research from the benchmark's earlier version (documented in arXiv:2605.10865) found that models typically recover coarse outer geometry accurately but fail on precise parametric features, standard-driven dimensions, and complex geometric operations like sweeps and lofts.

The internal model's 0.875 score represents a 47% relative improvement over Astra's 0.594 on this benchmark. OpenAI did not disclose the internal model's name, architecture, or availability timeline. The company disclosed the numbers without disclosing what they describe — a characteristic move that creates a credible capability signal without committing to a launch.

How GPT-6 Astra Compares on Third-Party AI Hardware Benchmarks

Third-party benchmark results situate Astra's hardware design capability in the broader landscape of AI models. EEBench places Astra at 69.3% on PCB routing tasks — described by evaluators as roughly the same ballpark as Claude Opus 5, albeit cheaper and faster on this specific task class.

The EEBench operators have a potential conflict of interest worth flagging: Atopile, which runs the benchmark, also develops AI-assisted KiCad PCB tools and has a commercial stake in the AI EDA ecosystem. The methodology and results remain useful for relative comparison, but the figures should be treated as directionally accurate rather than independently audited.

Artificial Analysis, which independently tracks frontier model performance, ranks GPT-6 Astra fifth among approximately 60 evaluated models on its Intelligence Index with a score of 57, indicating strong general reasoning capability without top-tier ranking. The hardware design task appears to push into areas where general reasoning does not fully compensate for domain-specific knowledge — particularly the physical constraints that DFM rules encode.

A 23x Token Surge Across OpenAI's Hardware Teams

The hardware device demonstration emerged as a side project. The broader trend it represents runs across OpenAI's own engineering organization.

Token consumption by OpenAI's hardware teams — groups working on robotics, compute infrastructure, and physical engineering — grew 23 times between February 2026 and October 2026. That growth rate reflects a shift in engineering workflow rather than an isolated experiment. OpenAI's forward-deployed engineer Grace Lam described the AI tools as having "sped up the path from concepts to engineered components," citing faster CAD revision cycles and automated conversion between 3D models and 2D manufacturing drawings.

External partner deployments point in the same direction. Chip Ganassi Racing, the professional motorsports team, has used OpenAI's tools to convert 3D scans of physical race car components directly into editable CAD models with accompanying 2D manufacturing drawings — a workflow that previously required skilled CAD operators working from scratch. Mazda's principal engineer Akihiro Nakata reported using Astra to explore aerodynamic nose shapes and analyze their impact on drag and downforce, work he described as giving designers "more freedom to explore vehicle shapes" by accelerating the aerodynamic feedback loop.

Traditional EDA Vendors Versus AI-Native Approaches

The commercial EDA (Electronic Design Automation) market — dominated by Cadence, Siemens, and Synopsys — has integrated AI assistance into existing workflows for years, primarily through training optimization, constraint-satisfaction improvements, and routing heuristics. Siemens' Fuse EDA AI Agent targets chip and PCB workflow automation within the established EDA software paradigm. Quilter, an independent tool, uses physics-driven reinforcement learning for PCB layout and can produce routable results in geometrically complex designs faster than traditional autorouters.

OpenAI's approach is architecturally different. Rather than adding AI capabilities to an existing EDA environment, the Codex-plus-Astra workflow treats the agent as the primary design tool, generating CAD programs and manufacturing outputs directly. This bypasses traditional EDA software entirely for the design phases where language models can operate — component selection, enclosure geometry, firmware, and initial PCB layout — before handing off to fabricators for the manufacturing compliance verification that iterative refinement currently requires.

Whether this represents a displacement of professional EDA tools or a new on-ramp that feeds into them remains unclear from a single demonstration. What is clear is that the competitive pressure on EDA vendors with straightforward, text-driven interfaces is now coming from an unexpected direction.

What the Internal Model Score Signals for Hardware Engineering Roles

A 47% benchmark improvement between GPT-6 Astra (0.594) and an unnamed internal model (0.875) on BenchCAD 2.0 carries workforce implications beyond the hardware design demonstration itself. At Astra's current level, AI-generated hardware designs require multiple manufacturing revision rounds and experienced DFM review — a role for senior hardware engineers. If the internal model's benchmark improvement translates proportionally to real manufacturing constraint satisfaction, the revision rounds could shorten substantially.

The progression visible in BenchCAD 2.0 follows the same trajectory AI showed in software engineering: initial tools that reduced boilerplate and sped up experienced practitioners, followed by systems capable of producing working first drafts that junior engineers once handled. The OpenAI demonstration suggests the first phase is already underway in hardware. The internal model score suggests the second phase is a development cycle away.

The specific failure mode on display — Astra producing geometrically valid but DFM-noncompliant designs — is itself informative. It means the limitation is not spatial or logical reasoning about physical objects; it is knowledge of fabricator-specific manufacturing rules and IPC standards that exist primarily in proprietary documentation rather than in the publicly available text that training corpora predominantly sample. That is a tractable problem for a model with better domain-specific training data and more agentic access to DRC verification tools during the design loop.

OpenAI has not announced when or whether the internal model that scored 0.875 on BenchCAD 2.0 will be released. What its benchmark result establishes is that the company considers hardware design capability a measurable, improvable property of its frontier models — and that it is already measuring it internally.