Micron Q4 FY2026 Earnings: The $50 Billion Test for the AI Memory Supercycle

Micron Technology reports fiscal fourth-quarter 2026 results on Wednesday, September 30, after the US market close, and the report arrives as the most consequential in the company's history. Guided at $50 billion in revenue — nearly double the previous quarter and more than four times the year-ago period — the print will be the single largest quarterly revenue number ever posted by a memory company. But for AI infrastructure, the number that will actually move markets is not Q4. It is whatever Sanjay Mehrotra says about Q1 FY2027, when investors will learn whether Micron's supply constraints extend through next year or begin to ease — and with them, the availability of every GPU cluster that depends on high-bandwidth memory.

The Q4 report is available for webcast at investors.micron.com beginning at 4:30 p.m. Eastern time (2:30 p.m. Mountain).

Three Consecutive Records Built the Runway to $50 Billion

Micron's fiscal Q3 2026, reported June 24, produced $41.46 billion in revenue — a 74% sequential jump and a 346% year-over-year increase — on non-GAAP gross margins of 84.9% and earnings per share of $25.11. Every single one of those figures had been a company record at the time. All four of Micron's business segments posted growth both sequentially and year-over-year, with data-center demand driving the majority of the gain.

The Q4 guidance issued on that call set a revenue midpoint of $50.0 billion, plus or minus $1 billion, with gross margins expected to expand further to approximately 86% and non-GAAP diluted EPS of $31.00, plus or minus $1.00. This is a 53-week fiscal year for Micron, meaning Q4 contains 14 weeks rather than the standard 13 — a roughly 7% sequential calendar tailwind that analysts will adjust for when comparing sequential results.

Wall Street expects Micron to match or modestly exceed that guidance. Consensus estimates as of September 26 cluster around $50.9 billion in revenue and $31.49 in non-GAAP EPS, both of which imply roughly 350% year-over-year growth. Goldman Sachs analyst James Schneider is projecting $51.9 billion, about 3% above consensus, alongside a gross margin of 87.3% and Q1 FY2027 revenue growing in the low-teens percentage sequentially. BMO Capital's Harsh Kumar, rated among the top analysts tracked by TipRanks, maintained a Buy rating heading into the report, citing supply checks indicating tight memory conditions persist at least through calendar 2027.

Why HBM4 Is Not a Memory Product — It Is an Accelerator Component

High-bandwidth memory has been called a commodity upgrade, but the architecture makes clear it is something fundamentally different. Where a DDR5 DIMM slots into a motherboard socket and can be swapped in an afternoon, HBM is integrated directly with the GPU or custom AI accelerator in what semiconductor engineers call a System-in-Package, or SiP.

The physical structure works as follows. Multiple DRAM dies — twelve in Micron's current flagship 36GB HBM4 product — are stacked vertically. Thousands of microscopic copper columns called Through-Silicon Vias, or TSVs, run through each die from top to bottom, creating a dense web of vertical connections. A logic base die sits at the bottom of the stack, managing the high-speed interface to the host processor. The entire stack then connects to a silicon interposer alongside the GPU die, creating a compact package where compute and memory sit microns apart rather than centimeters.

The most important consequence of this architecture is bandwidth. HBM4 runs a 2048-bit interface — double the 1024-bit width of its predecessor HBM3E — delivering speeds exceeding 2.0 terabytes per second per stack. A large Nvidia Vera Rubin accelerator package stacks multiple HBM4 units, pushing total system memory bandwidth into the tens of terabytes per second. By comparison, a consumer DDR5 memory channel delivers tens of gigabytes per second. This difference in bandwidth, not raw capacity, is why HBM4 is essential for AI inference: large-language-model inference spends significant time reading model weights and key-value cache data from memory, and the speed at which that data arrives at the compute die determines how quickly the system can generate output tokens.

Read more: Nvidia Posts First Vera Rubin Benchmark Data: 30x Efficiency Gain on Agentic Workloads

Micron's current HBM4 product is built on its 1-beta DRAM process node and is in high-volume shipment for its lead customer's accelerator platform — a reference that effectively identifies Nvidia's Vera Rubin, which Jensen Huang confirmed on June 5 had been certified with all three major HBM suppliers. Micron says it has already shipped more than $1 billion in HBM4 revenue, and that the HBM4 production ramp is tracking at twice the speed of the HBM3E ramp that preceded it.

Supply Locked, Demand Climbing: The Memory Crisis That Has No Scheduled End

Micron's CEO has been unusually direct about the supply-demand imbalance. On prior earnings calls, Mehrotra disclosed that Micron can currently fulfill only 50% to two-thirds of customer demand for its memory products. This is not a short-term constraint. The company says it has no line of sight as to when supply will be able to catch up with accelerating demand.

The structural reason for the gap is a production trade-off that most AI coverage ignores. As Micron's Raghu Sreeramaneni explained at Hot Chips 2026, every wafer Micron devotes to HBM production consumes roughly three times the silicon area that the equivalent number of standard DDR5 bits would require. This 3:1 wafer conversion ratio means every percentage point of HBM capacity growth directly compresses the supply available for server DDR5, mobile LPDDR5X, and consumer DRAM. The AI supercycle is not simply driving incremental demand — it is restructuring where every wafer in the global DRAM supply chain goes.

To address this, Micron has taken the unusual step of signing 16 strategic customer agreements, or SCAs, with data-center, consumer, and automotive customers. Fourteen of those 16 agreements carry cumulative minimum contracted revenue of approximately $100 billion over their remaining terms. According to Micron's 10-Q filing, the agreements are take-or-pay, meaning customers commit to purchasing specified volumes at agreed prices — or pay a penalty if they do not. Micron expects to receive approximately $22 billion in cash deposits and related financial commitments from these agreements, with roughly $18 billion in the form of cash deposits already committed. HBM3E and HBM4 are fully booked under these and earlier agreements through calendar 2027, with demand already extending into 2028.

This contract structure is new for the memory industry, which has historically been one of the most volatile commodity businesses in semiconductors. In past cycles, memory prices would collapse when new capacity came online. The SCA structure caps downside for Micron by establishing price floors and volume commitments, while customers gain supply certainty. It is a revealed preference: when hyperscalers voluntarily post billions in cash deposits for memory supply through 2030, they are signaling that supply risk — not price risk — is their primary concern.

Three Players, Unequal Positions, and a Chinese Entrant

The global HBM market has three serious participants, and their relative positions matter directly for how AI accelerator supply chains evolve. SK Hynix holds 56.4% of HBM revenue share as of the first quarter of 2026, according to IDC data cited in the company's SEC filings. It entered HBM4 qualification ahead of rivals and is the primary volume supplier for Nvidia's flagship accelerator systems. Samsung began HBM4 mass production in February 2026, holds an in-house logic node that gives it a potential advantage for the customized base-die designs that HBM4E will require, and was confirmed by Nvidia as certified for Vera Rubin. Micron is in third position by HBM market share but is gaining: its HBM4 ramp speed and the volume of customer certifications it is accumulating suggest it is narrowing the gap with Samsung in unit economics if not yet in allocation percentage.

Micron's path to competitive parity in the HBM base-die layer runs through TSMC. For HBM4E, its next-generation product targeted for calendar 2027, Micron has confirmed it will shift the logic base die from an in-house DRAM process to a TSMC foundry process. This is the same direction SK Hynix is taking. Both companies will use a leading-edge logic node to shrink the base die's power consumption and enable the custom configurations that AI accelerator customers are beginning to request — different cache sizes, routing logic, and protocol interfaces optimized for specific workloads. The customization layer is where HBM ceases to be a commodity component altogether and becomes an accelerator-specific co-design.

At the bottom of the competitive ladder is China's ChangXin Memory Technologies, or CXMT. Reporting from The Information indicates the company has begun small-scale production of HBM3E — a generation behind Micron, SK Hynix, and Samsung. CXMT cannot access extreme-ultraviolet lithography tools under current US export restrictions, which limits its manufacturing node advancement and raises production costs. For now, its primary pressure on Micron falls in commodity DRAM — mobile and server — rather than in HBM, where it trails by multiple generations and faces manufacturing constraints that cannot be resolved quickly. The longer-term concern is that CXMT's DRAM market share trajectory (from roughly 3% to 8% in approximately a year, per Counterpoint Research data) follows a pattern familiar from Chinese manufacturers in solar, batteries, and displays.

The Q4 Report and the Question That Actually Matters

Micron's Q4 results, when they land the evening of September 30, will be read primarily through one lens: what does Q1 FY2027 guidance say about the durability of the supercycle?

The Q4 numbers themselves are largely set. The high-volume HBM4 shipments that started in calendar Q1 2026, the contract structures locking in pricing, and the strong data-center DRAM environment mean the quarter will almost certainly exceed the $49 billion floor of guidance. The options market heading into the report is pricing approximately a 9.9% move in either direction, reflecting the binary nature of the forward outlook rather than uncertainty about Q4 itself.

What is genuinely uncertain is what Mehrotra says about 2027. If guidance for Q1 FY2027 points toward continued low-to-mid-teens sequential growth — consistent with Goldman Sachs and Wells Fargo models — and language on HBM supply constraints remains unchanged, the structural thesis that drove Micron's stock to gains exceeding 260% year-to-date before the report remains intact. If guidance softens, or if Mehrotra signals that HBM3E pricing has peaked, investors will treat it as an early signal that new memory capacity arriving in late 2027 and 2028 will erode the pricing floor faster than the SCA structures can compensate.

The memory wall that Micron's Sreeramaneni described at Hot Chips 2026 — compute capabilities growing at roughly 3x every two years while memory bandwidth grows at less than 2x over the same period — means the structural demand for HBM is not disappearing. But history in DRAM is clear: supply always catches up, and when it does, it often overshoots. Micron's SCA contracts provide a floor. They do not prevent the ceiling from arriving eventually. Whether that ceiling is 2027, 2028, or later depends on how quickly Micron, SK Hynix, and Samsung bring new fabrication capacity online — and how much of that capacity China's CXMT can displace in commodity tiers before the incumbents need to defend it.

September 30's most important number will not be written in the Q4 press release. It will be spoken on the call, in whatever language Mehrotra chooses when he describes how tightly HBM supply is booked and how far into 2027 and 2028 he can see committed demand. That forward visibility — not Q4's record revenue — is the data point that will tell AI infrastructure teams whether their planned GPU cluster expansions have the memory to support them.